Field of the Invention
The present invention relates to a semiconductor device and in particular to a metal diffusion barrier for electrical interconnections.
A semiconductor device commonly comprises a semiconductor substrate with a plurality of active areas on its surface and multiple metallization layers on top of that surface. The metallization layers are mutually separated by dielectric layers made of SiO.sub.2, Si.sub.3 N.sub.4, BPSG or other suitable materials and comprise a plurality of conductive tracks on top of the dielectric layers or in grooves which are formed on the surface of the dielectric layers. These conductive tracks define, in conjunction with contact openings through the dielectric layers, the interconnection structure of the semiconductor device.
To form such an interconnection structure a dielectric layer is deposited on top of the semiconductor substrate or on top of a metallization layer and subsequently anisotropically etched to form contact openings (vias) which extend through the dielectric layer to the metallization layer or to the substrate. In the next step, the vias are filled with an electrical conductive material such as tungsten or polysilicon. Finally, a metal layer is deposited on top of the dielectric layer and subsequently structured.
In another approach to form an interconnection structure grooves are additionally formed in the dielectric layer after the formation of the contact openings. The grooves which are partially in contact with the contact openings define the location of the conductive tracks. Preferably, the grooves and the contact openings are completely filled with a conductive material in one step. The conductive material is subsequently polished back to the top surface of the dielectric layer in order to obtain a plain surface with completely filled grooves. This method is called a dual damascene process.
The materials mainly used for the metallization are aluminum, tungsten and polysilicon. However, as the structuring size of the semiconductor device is scaled down to submicron dimensions, the electrical resistance of the vias and the conductive tracks increases due to the reduced cross-section of the conductive structures. To overcome this problem, the use of highly conductive materials such as copper (Cu) has been proposed. Unfortunately, copper tends to diffuse into the dielectric layer and the active areas of the semiconductor substrate and therefore has to be completely encapsulated by a metal diffusion barrier. An appropriate material for such a diffusion barrier is for instance tantalum (Ta) (see U.S. Pat. Nos. 5,714,418; 5,528,599, and 5,817,572).
Due to adhesion problems of tantalum to a variety of dielectric materials such as SiO.sub.2, an additional tantalum nitride layer (TaN) between the Ta and the dielectric layer has been suggested (see published European patent application EP 0 751 566 A2). Since TaN can only be deposited by a PVD process it is difficult to obtain a thin and highly conformal layer, which is very important for reliable interconnections of submicron size.